Throughout this application various publications are referenced. The disclosures of each of these publications in their entireties are hereby incorporated by reference in this application.
One of the primary objectives in semiconductor manufacturing is to produce lower cost integrated circuits (ICs) while at the same time develop devices with higher performance. The major factor affecting the device performance is the signal transmission rate within a device. Signals through metal interconnects are delayed by both the resistance (R) in the metal lines and the capacitance (C) of the inter-metal dielectric (IMD) material. This RC delay can be reduced in circuits by using metals with lower resistance than aluminum and by using low dielectric constant materials to replace SiO2. Copper has emerged as the metal of choice to reduce interconnect resistance. The transition of copper interconnect technology into IC manufacturing is underway.
Although copper interconnects offer advantages in performance, a need exists for an appropriate diffusion barrier/adhesion promoter for the copper interconnects. The conductive barrier materials currently used for aluminum metallization (Ti, TiN, W and nitrided W) have been investigated and found effective in preventing copper diffusion (Braud et. al., Microelectronic Engineering, 33:293 (1997)). Other coatings that have emerged as a suitable barrier for current generation IC circuits are Ta and TaN (Stavrev et al., Microelectronic Engineering 33:269(1997), Min et al., J. of Vacuum Science & Tech. B., 14(5):3263 (1996)). Unfortunately, as feature sizes shrink and aspect ratios increase to meet the microelectronic industries demand for improved device performance, the limitations of plasma vapor deposition (PVD) based Ti/TiN and Ta based liners becomes apparent.